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this is information on a product in full production. october 2014 docid15453 rev 12 1/52 stm6600, stm6601 smart push-button on/off cont roller with smart reset? and power-on lockout datasheet - production data features ? operating voltage 1.6 v to 5.5 v ? low standby current of 0.6 a ? adjustable smart reset ? assertion delay time driven by external c srd ? power-up duration determined primarily by push-button press (stm6600) or by fixed time period, t on_blank (stm6601) ? debounced pb and sr inputs ? pb and sr esd inputs withstand voltage up to 15 kv (air discharge) 8 kv (contact discharge) ? active high or active low enable output option (en or en) provides control of mosfet, dc-dc converter, regulator, etc. ? secure startup, in terrupt, smart reset ? or power-down driven by push-button ? precise 1.5 v voltage reference with 1% accuracy ? industrial operating temperature ?40 to +85 c ? available in tdfn12 2 x 3 mm package applications ? portable devices ? termin als ? audio and video players ? cell phones and smart phones ? pdas, palmtops, organizers 7')1 table 1. device summary device rst c srd pb / sr en or en int startup process stm6600 open drain (1) 1. external pull-up resistor needs to be connected to open drain outputs. ?? push-pull open drain (1) pb must be held low until the ps hold (2) confirmation 2. for a successful startup, the ps hold (power supply hold) needs to be pull ed high within specific time, t on_blank . stm6601 open drain (1) ?? push-pull open drain (1) pb can be released before the ps hold (2) confirmation www.st.com
contents stm6600, stm6601 2/52 docid15453 rev 12 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
docid15453 rev 12 3/52 stm6600, stm6601 list of tables 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6. tdfn12 (2 x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7. carrier tape dimensions for tdfn12 (2 x 3 mm) pa ckage . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 8. stm6600 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 9. stm6601 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 10. stm6600 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 11. stm6601 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
list of figures stm6600, stm6601 4/52 docid15453 rev 12 list of figures figure 1. application hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. basic functionality (option with enable deasserti on after long push) . . . . . . . . . . . . . . . . . . 6 figure 3. basic functionality (option with rst assertion after long push) . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. tdfn12 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. successful power-up on stm6600 (pb released prior to t on_blank expiration) . . . . . . . . 14 figure 8. successful power-up on stm6600 (t on_blank expires prior to pb release) . . . . . . . . . . . 15 figure 9. unsuccessful power-up on stm6600 (pb released prior to t on_blank ) . . . . . . . . . . . . . . 16 figure 10. unsuccessful power-up on stm6600 (t on_blank expires prior to pb release) . . . . . . . . . 17 figure 11. successful power-up on stm6601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 12. unsuccessful power-up on stm6601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. power-up on stm660x with voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. pb interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. long push, pb pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16. long push, sr pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17. invalid long push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18. long push (option with rst assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19. long push (option with enable deassertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 20. undervoltage detected for t srd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 22. pb out output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23. supply current vs. temperature, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 24. supply current vs. temperature, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 25. supply current vs. supply voltage, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 26. supply current vs. supply voltage, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 27. threshold vs. temperature, v th+ = 3.4 v (typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 28. threshold hysteresis vs. temperature, v hyst = 200 mv (typ.) . . . . . . . . . . . . . . . . . . . . . . 30 figure 29. debounce period vs. supply voltag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 30. c srd charging current vs. temperature, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 31. output low voltage vs. output low current, t a = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 32. output high voltage vs. output high current, t a = 25 c. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 33. output voltage vs. supply voltage, i out = 1 ma, t a = 25 c . . . . . . . . . . . . . . . . . . . . . . . 33 figure 34. input voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 35. reference output voltage vs. temperature, v cc = 2.0 v. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 36. reference output voltage vs. load current, v cc = 2.0 v, t a = 25 c . . . . . . . . . . . . . . . . . 34 figure 37. reference output voltage vs. supply voltage, t a = 25 c. . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 38. reference startup, i ref = 15 f, t a = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 39. reference response to steps on supply voltage, i ref = 15 a, t a = 25 c . . . . . . . . . . . . 36 figure 40. reference response to steps in load current, v cc = 3.6 v, t a = 25 c . . . . . . . . . . . . . . . 37 figure 41. tdfn12 (2 x 3 mm) package outlin e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 figure 42. tdfn12 (2 x 3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 43. carrier tape for tdfn12 (2 x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
docid15453 rev 12 5/52 stm6600, stm6601 description 51 1 description the stm6600-01 devices monitor the state of connected push-button(s) as well as sufficient supply voltage. an enable output controls power for the application through the mosfet transistor, dc-dc converter, regulator, etc. if the supply voltage is above a precise voltage threshold, the enable output can be asserted by a simple press of the button. factory-selectable supply voltage thresholds are determined by highly accurate and temperature-compensated references. an interrupt is asserted by pressing the push-button during normal operation and can be used to request a system power-down. the interrupt is also asserted if undervoltage is detected. by a long push of one button ( pb ) or two buttons ( pb and sr ) either a reset is asserted or power fo r the application is disabled depending on the option used. the device also offers additional features su ch as precise 1.5 v voltage reference with very tight accuracy of 1%, separate output indica ting undervoltage detecti on and separate output for distinguishing between interrupt by push-button or undervoltage. the device consumes very low current of 6 a during normal operation and only 0.6 a current during standby. the stm6600-01 is available in the tdfn12 pa ckage and is offered in several options among features such as selectable threshol d, hysteresis, timeouts, output types, etc. figure 1. application hookup 1. a resistor is required for open drain output type only. a 10 k pull-up is sufficient in most applications. 2. capacitor c ref is mandatory on v ref output (even if v ref is not used). capacitor value of 1 f is recommended. 3. for the stm6601 the processor has to confirm th e proper power-on during the fixed time period, t on_blank . this failsafe feature prevents the user from turning on the system when there is a faulty power switch or an unresponsive microprocessor. 670 670 3% 287 9 5() 9&& /2 3% 9 && 65 *1' ,17 36 +2/' 567 & 65' (1(1 '&'& frqyhuwhu srzhu026)(7 uhjxodwruhwf /(' 5 & 65' & 5() 5 5 $0y %$6(%$1' 567 ,2 10,ru,17 ,2 9 '' 0&8 &38 5 670 670 3% 287 9 5() 9&& /2 3% 9 && 65 *1' ,17 36 +2/' 567 & 65' (1(1 '&'& frqyhuwhu srzhu026)(7 uhjxodwruhwf /(' 5 & 65' & 5() 5 5 $0y %$6(%$1' 567 ,2 10,ru,17 ,2 9 '' 0&8 &38 5
description stm6600, stm6601 6/52 docid15453 rev 12 figure 2. basic functionality (option with enable deassertion after long push) 1. for power-up the battery voltage has to be above v th+ threshold. figure 3. basic functionality (option with rst assertion after long push) 1. for power-up the battery voltage has to be above v th+ threshold. figure 4. logic diagram pb sr power-up (1) interrupt (short push) power-down (long push) en int interrupt interrupt am00243v1 pb power-up (1) interrupt (short push) power-down (long push) sr int interrupt interrupt rst am00243bv1 am00236v1 stm6600 stm6601 rst gnd c srd int ps hold v cc pb out vcc lo v ref en (en) sr pb
docid15453 rev 12 7/52 stm6600, stm6601 description 51 figure 5. tdfn12 pin connections table 2. pin descriptions pin number symbol function 1v cc power supply input 2sr smart reset ? button input 3v ref precise 1.5 v voltage reference 4ps hold ps hold input 5c srd adjustable smart reset ? delay time input 6pb push-button input 7vcc lo output for high thres hold comparator output (v th+ ) 8pb out status of pb push-button input 9en or en enable output 10 rst reset output 11 int interrupt output 12 gnd ground am00245v1 gnd c srd ps hold v cc en (en) rst int 5 1 4 8 67 9 10 11 12 3 2 pb out sr v ref pb vcc lo
description stm6600, stm6601 8/52 docid15453 rev 12 figure 6. block diagram 1. internal pull-up resistor connected to pb input (see table 5 for precise s pecifications). 2. optional internal pull- up resistor connected to sr input (see table 5 for precise specifications and table 10 for detailed device options). 3. internal pull-down resistor is connected to ps hold input only during startup (see figure 7 , 8 , 9 , 10 , 11 , 12 , 13 , and 18 ). v th+ pb en (en) smart logic edge detector debounce srd logic gnd c srd t rec generator int rst ps hold v cc vcc lo v ref glitch immunity pb out am00237v3 1.5 v edge detector debounce glitch immunity + ? v th? + ? sr r pshold (3) v cc v cc r pb r sr (1) (2)
docid15453 rev 12 9/52 stm6600, stm6601 pin descriptions 51 2 pin descriptions v cc - power supply input v cc is monitored during startup and normal oper ation for sufficient voltage level. decouple the v cc pin from ground by placing a 0.1 f capacitor as close to the device as possible. sr - smart reset ? button input this input is equipped with voltage detector wit h a factory-trimmed threshold and has 8 kv hbm esd protection. both pb and sr buttons have to be pressed and held for t srd period so the long push is recognized and the reset is asserted (or the enable output is deasserted depending on the option) - see figure 15 , 16 , and 17 . active low sr input is usually connected to gnd th rough the momentary push-button (see figure 1 ) and it has an optional 100 k pull-up resistor. it is also possible to dr ive this input using an external device with either open drain (recommended) or push-pull output. open drain output can be connected in parallel with push-button or other open drain outputs, which is not possible with push-pull output. sr input is monitored for falling edge after power-up and must not be grounded permanently. v ref - external precise 1.5 v voltage reference this 1.5 v voltage reference is specif ied with very tight accuracy of 1% (see table 5 ). it has proper output voltage as soon as the reset output is deasserted (i.e. after t rec expires) and it is disabled when the device enters stan dby mode. a mandatory capacitor needs to be connected to v ref output (even if v ref is not used). capacitor value of 1 f is recommended. ps hold input this input is equipped with a voltage detector wi th a factory-trimmed threshold. it is used to confirm correct power-up of the device (if en or en is not asserted) or to initiate a shutdown (if en or en is asserted). forcing ps hold high during power-up confirms the proper start of the application and keeps enable output asserted. because most proces sors have outputs in high-z state before initialization, an internal pull- down resistor is connected to ps hold input during startup (see figure 7 , 8 , 9 , 10 , 11 , 12 , 13 , and 18 ). forcing the ps hold signal low during normal operation deasserts the enable output (see figure 14 ). input voltage on this pin is compared to an accurate voltage reference. c srd - smart reset ? delay time input a capacitor to ground determines the additional time (t srd ) that pb with sr must be pressed and held before a long push is recognized. the connected c srd capacitor is charged with i srd current. additional smart reset ? delay time t srd ends when voltage on the c srd capacitor reaches the v srd voltage threshold. it is recommended to use a low esr capacitor (e.g. ceramic). if the capacitor is not used, leave the c srd pin open. if no capacitor is connected, there is no t srd and a long push is recognized right after t int _min expires (see figure 18 and 19 ).
pin descriptions stm6600, stm6601 10/52 docid15453 rev 12 pb - power on switch this input is equipped with a voltage detector with a factory-trimmed threshold and has 8 kv hbm esd protection. when the pb button is pressed and held, the battery voltage is detected and en (or en ) is asserted if the battery voltage is above the threshold v th+ during the whole t debounce period (see figure 13 ). a short push of the push-button during normal operation can initiate an interrupt through debounced int output (see figure 14 ) and a long push of pb and sr simultaneously can either assert reset output rst (see figure 18 ) or deassert the en or en output (see figure 19 ) based on the option used. note: a switch to gnd must be connected to this input (e.g. mechanical push-button, open drain output of external circuitry, etc.), see figure 1 . this ensures a proper startup signal on pb (i.e. a transition from full v cc below specified v il ). pb input has an internal 100 k pull-up resistor connected. vcc lo - high threshold detection output during power-up, vcc lo is low when v cc supply voltage is below the v th+ threshold. after successful power-up (i.e. during normal operation) vcc lo is low anytime undervoltage is detected (see figure 13 ). output type is active low and open drain by default. open drain output type requires a pull- up resistor. a 10 k is sufficient in most applications. vcc lo is floating when stm660x is in standby mode. pb out - pb input state if the push-button pb is pressed, the pin stays low during the t debounce time period. if pb is asserted for the entire t debounce period, pb out will then stay low for at least t int _min . if pb is asserted after t int _min expires, pb out will return high as soon as pb is deasserted (see figure 22 ). pb out ignores pb assertion during an undervoltage condition. at startup on the stm6601 pb out will respond only to the first pb assertion and any other assertion will be ignored until t on_blank expires. this output is active low and open drain by default. open drain output type requires a pull-up resistor. a 10 k is sufficient in most applications.
docid15453 rev 12 11/52 stm6600, stm6601 pin descriptions 51 en or en - enable output this output is intended to enable system power (see figure 1 ). en is asserted high after a valid turn-on event has been detected and confirmed (i.e. push-button has been pressed and held for t debounce or more and v cc > v th+ voltage level has been detected - see figure 13 ). en is released low if any of the conditions below occur: a) the push-button is released before ps hold is driven high (valid for stm6600, see figure 9 ) or t on_blank expires before ps hold is driven high during startup (valid for both stm6600 and stm6601, see figure 10 and 12 ). b) ps hold is driven low during normal operation (see figure 14 ). c) an undervoltage condition is detected for more than t srd + t int _min + t debounce (see figure 21 ). d) a long push of the buttons is detec ted (only for the devi ce with option ?en deasserted by long push? - see figure 19 ) or ps hold is not driven high during t on_blank after a long push of the buttons (only for the device with option ?rst asserted by long push? - see figure 18 ). described logic levels are inverted in case of en output. output type is push-pull by default. rst - reset output this output pulls low for t rec : a) during startup. pb has been pressed (f alling edge on the pb detected) and held for at least t debounce and v cc > v th+ (see figure 7 , 8 , 9 , 10 , 11 , 12 and 13 for more details). b) after long push detection (valid only for the device with option ?rst asserted by long push?). pb has been pressed (f alling edge on the pb detected) and held for more than t debounce + t srd (additional smart reset ? delay time can be adjusted by the external capacitor c srd ) - see figure 18 . output type is active low and open drain by default. open drain output type requires a pull- up resistor. a 10 k is sufficient in most applications. int - interrupt output while the system is under normal operation (ps hold is driven high, power for application is asserted), the int is driven low if: a) v cc falls below v th- threshold (i.e. undervoltage is detected - see figure 20 and 21 ). b) the falling edge on the pb is detected and the push-button is held for t debounce or more. int is driven low after t debounce and stays low as long as pb is held. the int signal is held high during power-up. the state of the pb out output can be used to determine if the interrupt was caused by either the assertion of the pb input, or was due to the detec tion of an undervoltage condition on v cc . int output is asserted low for at least t int _min . output type is active low and open drain by default. open drain output type requires a pull- up resistor. a 10 k is sufficient in most applications. gnd - ground
operation stm6600, stm6601 12/52 docid15453 rev 12 3 operation the stm6600-stm6601 simplified smart push-bu tton on/off controller with smart reset ? and power-on lockout enables and disables power for the application depending on push- button states, signals from the processor, and battery voltage. power-on because most of the processors have outputs in high-z state before initia lization, an internal pull-down resistor is connected to ps hold input during startup (see figure 7 , 8 , 9 , 10 , 11 , 12 , 13 , and 18 ). to power up the device the push-button pb has to be pressed for at least t debounce and v cc has to be above v th+ for the whole t debounce period. if the battery voltage drops below v th+ during the t debounce , the counter is reset and starts to count again when v cc > v th+ (see figure 13 ). after t debounce the enable signal is as serted (en goes high, en goes low), reset output rst is asserted for t rec and then the startup routine is performed by the processor. during initialization, the processor sets the ps hold signal high. on the stm6600 the ps hold signal has to be set high prior to push-button release and t on_blank expiration, otherwise the enable si gnal is deasserted (en goes low, en goes high) - see figure 7 , 8 , 9 , and 10 . the time up to push-button release represents the maximum time allowed for the system to powe r up and initialize the circuits driving the ps hold input. if the ps hold signal is low at push-button release, the enable output is deasserted immediately, thus turning off the system power. if t on_blank expires prior to push-button release, the ps hold state is checked at its expi ration. this sa fety feature disables the power and prevents discharging the battery if the push-butto n is stuck or it is held for an unreasonable period of time and the application is not responding (see figure 8 and 10 ). pb status, int status and v cc undervoltage detection are not monitored until power-up is completed. on the stm6601 the ps hold signal has to be set high before t on_blank expires, otherwise the enable signal is deasserted - see figure 11 and 12 . in this case the t on_blank period is the maximum time allowed for the power switch and processor to perform the proper power- on. if the ps hold signal is low at the end of the blanking period, the enable output is released immediately, thus turning off the system power. pb status, int status and v cc undervoltage detection are not monitored during the entire t on_blank period. this failsafe feature prevents the user from turning on the syst em when there is a faulty power switch or an unresponsive microprocessor. push-button interrupt if the device works under normal operation (i.e. ps hold is high) and the push-button pb is pressed for more than t debounce , a negative pulse with minimum t int _ min width is generated on the int output. by connecting int to the processor interrupt input ( int or nmi ) a safeguard routine can be performed and the power can be shut down by setting ps hold low - see figure 14 . forced power-down mode the ps hold output can be forced low anytime duri ng normal operation by the processor and can deassert the enable signal - see figure 14 .
docid15453 rev 12 13/52 stm6600, stm6601 operation 51 undervoltage detection if v cc voltage drops below v th- voltage threshold during normal operation, the int output is driven low (see figure 20 and figure 21 ). if an undervoltage condition is detected for t debounce + t int _min + t srd , the enable output is deasserted (see figure 21 ). hardware reset or power-down while system not responding if the system is not responding and the system hangs, the pb and sr push-buttons can be pressed simultaneously longer than t debounce + t int _min + t srd , and then a) either the reset output rst is asserted for t rec and the processor is reset (valid only for the device with option ?rst asserted by long push?) ? see figure 18 b) or the power is disabled by en or en signal (valid only for the device with option ?en deasserted by long push?) ? see figure 19 the t srd is set by the external capacitor connected to the c srd pin. sr input is monitored for falling edge after power-up and must not be grounded permanently. standby if the enable output is deasserted (i.e. en is low or en is high), the stm660x device enters standby mode with low current consumption (see table 5 ). in standby mode pb input is only monitored for the falling edge. th e external 1.5 v voltage refe rence is also disabled in standby mode.
waveforms stm6600, stm6601 14/52 docid15453 rev 12 4 waveforms figure 7. successful power-up on stm6600 (pb released prior to t on_blank expiration) 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k is connected to ps hold input during power-up. 3. en signal is high even after pb release, because processor sets ps hold signal high before pb is released. ps hold ignored internal pull-down resistor connected to ps hold input v cc undervoltage detection ignored pb (1) ps hold (2) en (3) rst push-button pressed and pb connected to gnd t debounce t rec processor sets ps hold pb released prior to t on_blank expiration ps hold state detected as high en remains asserted t on_blank am00247v 3 int signal is held high during power-up (i.e. until pb release in this case). v cc is considered v cc > v th+ . note:
docid15453 rev 12 15/52 stm6600, stm6601 waveforms 51 figure 8. successful power-up on stm6600 (t on_blank expires prior to pb release) 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k is connected to ps hold input during power-up. 3. t on_blank expires prior to pb release so ps hold is checked at its expiration. ps hold ignored internal pull-down resistor connected to ps hold input v cc undervoltage detection ignored pb (1) ps hold (2) en (3) rst push-button pressed and pb connected to gnd t debounce t rec processor sets ps hold pb released t on_blank t on_blank expired prior to pb release ps hold state detected as high en remains asserted am00247 b v2 int signal is held high during power-up (i.e. until t on_blank expires in this case). v cc is considered v cc > v th+ . note:
waveforms stm6600, stm6601 16/52 docid15453 rev 12 figure 9. unsuccessful power-up on stm6600 (pb released prior to t on_blank ) 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k is connected to ps hold input during power-up. 3. en signal goes low with pb release, because processor did not force ps hold signal high. internal pull-down resistor connected to ps hold input ps hold ignored pb status ignored v cc undervoltage detection ignored pb (1) ps hold (2) en (3) rst push-button pressed and pb connected to gnd t debounce pb released ps hold state detected as low en deasserted t rec t en_off t on_blank am0024 8 v 3 int signal is held high during power-up (i.e. until pb release in this case). v cc is considered v cc > v th+ . note:
docid15453 rev 12 17/52 stm6600, stm6601 waveforms 51 figure 10. unsuccessful power-up on stm6600 (t on_blank expires prior to pb release) 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k is connected to ps hold input during power-up. 3. t on_blank expires prior to pb release so ps hold is checked at its expiration. internal pull-down resistor connected to ps hold input ps hold ignored pb status ignored v cc undervoltage detection ignored pb (1) ps hold (2) en (3) rst push-button pressed and pb connected to gnd t debounce pb released t rec t en_off t on_ blank t on_blank expired prior to pb release ps hold state detected as low en is deasserted am0024 8b v2 int signal is held high during power-up (i.e. until t on_blank expires in this case). v cc is considered v cc > v th+ . note:
waveforms stm6600, stm6601 18/52 docid15453 rev 12 figure 11. successful power-up on stm6601 1. pb detection on falling edge. 2. internal pull-down resistor 300 k is connected to ps hold input during power-up. 3. ps hold signal is ignored during t on_blank . when t on_blank expires, the level of the ps hold signal is high therefore the en signal remains asserted. pb status and v cc undervoltage ignored pb (1) en (3) rst push-button pressed and pb connected to gnd t debounce t rec processor sets ps hold detection t on_blank ps hold ignored t on_blank expires ps hold state detected as high en remains asserted (2) internal pull-down resistor connected to ps hold input ps hold am00250v2 int signal is held high during power-up (i.e. until t on_blank expires in the case of the stm6601). v cc is considered v cc > v th+ . note:
docid15453 rev 12 19/52 stm6600, stm6601 waveforms 51 figure 12. unsuccessful power-up on stm6601 1. pb detection on falling edge. 2. internal pull-down resistor 300 k is connected to ps hold input during power-up. 3. ps hold signal is ignored during t on_blank . when t on_blank expires, the level of the ps hold signal is not high therefore the en signal goes low. even releasing the pb button after the t on_blank will not prevent this. en (3) (2) t on_blank expires ps hold state detected as low en deasserted intenal pull-down resistor connected to ps hold input t debounce push-button pressed and pb connected to gnd push-button pressed and pb connected to gnd t rec pb (1) rst ps hold ignored ps hold am00238v2 int signal is held high during power-up (i.e. until t on_blank expires in the case of the stm6601). v cc is considered v cc > v th+ . note:
waveforms stm6600, stm6601 20/52 docid15453 rev 12 figure 13. power-up on stm660x with voltage dropout 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k is connected to ps hold input during power-up. 3. int signal is held high during power-up. v cc goes above v th+ and t debounce is counted again v th? v cc under- voltage detected v cc drop v th+ v cc vcc lo pb (1) en t debounce t rec < t on_blank int signal is held high during power-up ps hold (2) rst push-button pressed and pb connected to gnd < t debounce int (3) internal pull-down resistor connected to ps hold input v cc?min am00249v2
docid15453 rev 12 21/52 stm6600, stm6601 waveforms 51 figure 14. pb interrupt 1. pb detection on falling edge. pb (1) t debounce t int_min t en_off push-button pressed and pb connected to gnd and en is deasserted accordingly pb status ignored v cc undervoltage detection ignored pb status ignored processor sets ps hold low ps hold am00251v2 processor interrupt starts power-down sequence note: v cc is considered v cc > v th+ .
waveforms stm6600, stm6601 22/52 docid15453 rev 12 figure 15. long push, pb pressed first figure 16. long push, sr pressed first pb status ignored pb int push-button pb is pressed t debounce t int_min sr t debounce push-button sr is pressed t srd starts to be counted am00257v1 t srd set by c srd pb status ignored pb int push-button pb is pressed t debounce t int_min sr push-button sr is pressed t srd starts to be counted t srd set by c srd am00258v1
docid15453 rev 12 23/52 stm6600, stm6601 waveforms 51 figure 17. invalid long push pb status ignored any rising edge will stop t srd to count regardless of glitch immunity am00259v1 pb int push-button pb is pressed t debounce t int_min sr push-button sr is pressed t srd starts to be counted set by c srd < t srd
waveforms stm6600, stm6601 24/52 docid15453 rev 12 figure 18. long push (option with rst assertion) 1. t srd period is set by external capacitor c srd . 2. pb ignored during t int _min . 3. ps hold signal is ignored during t on_blank . its level is checked after t on_blank expires and if it is high the en signal remains asserted, otherwise en goes low. 4. internal pull-down resistor 300 k is connected to ps hold input during startup when device is reset. intern a l p u ll-down re s i s tor connected to p s hold inp u t p s hold ignored pb s t a t us ignored t on_blank t s r d (1) s et b y c s rd v cc u ndervolt a ge detection s t a t us ignored pb p s hold ( 3 , 4) int (2) r s t p us h- bu tton pre ss ed a nd pb connected to gnd t debounce t rec p us h- bu tton held even a fter t s rd expire s therefore r s t i s ass erted int c a n go high , if pb goe s high, bu t s y s tem freeze s a nd proce ss or won?t re s pond if s y s tem freeze s , proce ss or won?t re s pond to a ny int s t a t us ch a nge t int _ min t debounce after t on_blank pb i s monitored for f a lling edge t on_ blank expire s p s hold s t a te detected as high therefore en rem a in s high (v a lid for s tm6600 a nd s tm6601) s r am00252v2 note: en is high.
docid15453 rev 12 25/52 stm6600, stm6601 waveforms 51 figure 19. long push (option with enable deassertion) 1. t srd period is set by external capacitor c srd . 2. pb ignored during t int _min . 3. after t srd expires en is forced low. pb s t a t us ignored pb s t a t us ignored v cc u ndervolt a ge detection s t a t us ignored pb p s hold int (2) en ( 3 ) p us h- bu tton pre ss ed a nd pb connected to gnd t debounce p us h- bu tton held even a fter t s rd expire s a nd en i s de ass erted t int _ min t debounce after t en_off expire s pb i s monitored for f a lling edge t en _ off int c a n go high, if pb goe s high, bu t s y s tem freeze s a nd proce ss or won?t re s pond if s y s tem freeze s , proce ss or won?t re s pond to a ny int s t a t us ch a nge t s rd (1) s et b y c s rd s r am0025 3 v2
waveforms stm6600, stm6601 26/52 docid15453 rev 12 figure 20. undervoltage detected for t srd 1. after t srd expires v cc is still insufficient (below v th+ ) thus power is disabled (en goes low or en goes high). 2. t srd period is set by external capacitor c srd . pb status ignored v cc under- v oltage detection ignored v cc-min vcc lo v cc (1) en and en is deasserted accordingly pb status ignored processor interrupt starts power-down sequence processor sets ps hold low t srd (2) set by c srd t debounce t int_min t en_off int v cc undervoltage detected v th+ v th ? ps hold am00254v1 en vcc lo v cc-min pb status ignored v cc is below v th+ even after t srd expires thus power is disabled (en goes low) and pb is monitored for regular startup v cc under- voltage detection ignored int ps hold v cc undervoltage detected v th+ v th ? v cc (1) pb status ignored t debounce t int_min t en_off t srd (2) set by c srd am00255v1
docid15453 rev 12 27/52 stm6600, stm6601 waveforms 51 figure 22. pb out output waveform 1. pulses on pb shorter than glitch immunity are ignored. 2. pulses on pb shorter than t debounce are not recognized by pb out . 3. minimum pulse width on pb out is t int _min . 4. if push-button is held longer than t debounce + t int _min , pb out goes high when the push-button is released. pb (1,2,3,4) typical operating characteristics stm6600, stm6601 28/52 docid15453 rev 12 5 typical operating characteristics figure 23. supply current vs. temperature, normal state figure 24. supply current vs. temperature, standby state 3 .0 3 .5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -40 -20 0 20 40 60 8 0 temper a t u re, t a (c) su pply c u rrent, i cc (a) v cc = 5.5 v v cc = 3 .6 v v cc = 2.0 v am04701v1 0.0 0.5 1.0 1.5 2.0 -40 -20 0 20 40 60 8 0 temper a t u re, t a (c) su pply c u rrent, i cc (a) v cc = 5.5 v v cc = 3 .6 v v cc = 2.0 v am04702v1
docid15453 rev 12 29/52 stm6600, stm6601 typical operating characteristics 51 figure 25. supply cu rrent vs. supply voltage, normal state figure 26. supply current vs. supply voltage, standby state 0 1 2 3 4 5 6 7 2.0 2.5 3 .0 3 .5 4.0 4.5 5.0 5.5 su pply volt a ge, v cc (v) su pply c u rrent, i cc (a) t a = 8 5 c t a = 25 c t a = 0 c t a = ?40 c am0470 3 v1 0.0 0.5 1.0 1.5 2.0 2.5 3 .0 3 .54.04.55.05.5 su pply volt a ge, v cc (v) su pply c u rrent, i cc (a) t a = 8 5 c t a = 25 c t a = 0 c t a = ?40 c am04704v1
typical operating characteristics stm6600, stm6601 30/52 docid15453 rev 12 figure 27. threshold vs. temperature, v th+ = 3.4 v (typ.) figure 28. threshold hysteresis vs. temperature, v hyst = 200 mv (typ.) 3 .20 3 .25 3 . 3 0 3 . 3 5 3 .40 3 .45 3 .50 -40 -20 0 20 40 60 8 0 temper a t u re, t a (c) thre s hold, v th+ (v) am04705v1 170 1 8 0 190 200 210 220 2 3 0 -40 -20 0 20 40 60 8 0 temper a t u re, t a (c) thre s hold hy s tere s i s , v hty s t (mv) am04706v1
docid15453 rev 12 31/52 stm6600, stm6601 typical operating characteristics 51 figure 29. debounce period vs. supply voltage figure 30. c srd charging current vs. temperature, v cc = 3.6 v 15 20 25 3 0 3 5 40 45 3 .544.555.5 su pply volt a ge, v cc (v) de b o u nce period, t debounce (m s ) t a = 8 5 c t a = 25 c t a = 0 c t a = ?40 c am04707v1 100 110 120 1 3 0 140 150 160 170 1 8 0 190 200 -40 -20 0 20 40 60 8 0 temper a t u re, t a (c) c s rd ch a rging c u rrent, i s rd (na) v cc = 5.5 v v cc = 3 .6 v v cc = 2 v am0470 8 v1
typical operating characteristics stm6600, stm6601 32/52 docid15453 rev 12 figure 31. output low voltag e vs. output low current, t a = 25 c note: characteristics valid for all the outputs (en, en , rst, int , pb out and vcc lo ). figure 32. output high voltage vs. output high current, t a = 25 c note: characteristics valid for en and en outputs. 0.00 0.05 0.10 0.15 0.20 0.25 0. 3 0 012 3 45 o u tp u t low c u rrent, i ol (ma) o u tp u t low volt a ge, v ol (v) v cc =1.6v v cc = 3 .6v v cc =5.5v am04709v1 0 0.2 0.4 0.6 0. 8 00.511.52 o u tp u t high c u rrent, i oh (ma) o u tp u t high volt a ge, v cc - v oh (v) v cc =1.6v v cc = 3 .6v v cc =5.5v am04710v1
docid15453 rev 12 33/52 stm6600, stm6601 typical operating characteristics 51 figure 33. output voltage vs. supply voltage, i out = 1 ma, t a = 25 c note: characteristics valid for all the outputs (en, en , rst, int , pb out and vcc lo ). figure 34. input voltage vs. temperature note: characteristics valid for pb , sr and ps hold inputs. 0 0.2 0.4 0.6 0. 8 1 012 3 45 su pply volt a ge, v cc (v) o u tp u t volt a ge, v out (v) am04711v1 0.99 1.00 1.01 1.02 1.0 3 1.04 1.05 -40 -20 0 20 40 60 8 0 temper a t u re, t a (c) inp u t volt a ge, v in (v) v cc = 3 .6 v v cc = 5.5 v am04712v1
typical operating characteristics stm6600, stm6601 34/52 docid15453 rev 12 figure 35. reference output voltage vs. temperature, v cc = 2.0 v note: 1 f capacitor is connected to the v ref pin. figure 36. reference output voltage vs. load current, v cc = 2.0 v, t a = 25 c note: 1 f capacitor is connected to the v ref pin. 1.4 8 0 1.4 8 5 1.490 1.495 1.500 1.505 1.510 1.515 1.520 -40 -20 0 20 40 60 8 0 temper a t u re, t a (c) reference o u tp u t volt a ge, v ref (v) i ref = 0 ma i ref = 15 a am0471 3 v1 1 1.1 1.2 1. 3 1.4 1.5 1.6 050100150200250 3 00 lo a d c u rrent, i ref (a) reference o u tp u t volt a ge, v ref (v) am04714v1
docid15453 rev 12 35/52 stm6600, stm6601 typical operating characteristics 51 figure 37. reference output voltage vs. supply voltage, t a = 25 c note: 1 f capacitor is connected to the v ref pin. figure 38. reference startup, i ref = 15 f, t a = 25 c note: 1 f capacitor is connected to the v ref pin. 1.4 8 0 1.4 8 5 1.490 1.495 1.500 1.505 1.510 1.515 1.520 22.5 33 .5 4 4.5 5 5.5 su pply volt a ge, v cc (v) reference o u tp u t volt a ge, v ref (v) i ref = 0 a i ref = 15 a am04715v1
typical operating characteristics stm6600, stm6601 36/52 docid15453 rev 12 figure 39. reference response to steps on supply voltage, i ref = 15 a, t a = 25 c note: 1 supply voltage goes from 3.6 v to 5.5 v and back to 3.6 v, ramp 1 v / 100 ns. 2 1 f capacitor is connected to the v ref pin.
docid15453 rev 12 37/52 stm6600, stm6601 typical operating characteristics 51 figure 40. reference response to steps in load current, v cc = 3.6 v, t a = 25 c note: 1 supply voltage goes from 0 a to 15 a and back to 0 a, ramp 1 a / 100 ns. 2 1 f capacitor is connected to the v ref pin.
maximum ratings stm6600, stm6601 38/52 docid15453 rev 12 6 maximum ratings stressing the device above the rating listed in table 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in table 4 of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. table 3. absolute maximum ratings symbol parameter min. max. unit remarks v cc input supply voltage ?0.3 +7.0 v input voltages on pb , sr , ps hold and c srd ?0.3 v cc + 0.3 v output voltages on en (en ), rst and int ?0.3 v cc + 0.3 v v esd electrostatic protection ?2 +2 kv human body model (all pins) ?8 +8 kv human body model (pb and sr ) v esd electrostatic protection ?1000 +1000 v charged device model v esd electrostatic protection ?200 +200 v machine model v esd point discharge on pb and sr inputs ?8 +8 kv iec61000-4-2 v esd air discharge on pb and sr inputs ?15 +15 kv iec61000-4-2 t a operating ambient temperature ?40 +85 c t stg storage temperature ?45 +150 c t sld (1) lead solder temperature for 10 seconds +260 c ja thermal resistance (junction to ambient) +132.4 c/w 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds.
docid15453 rev 12 39/52 stm6600, stm6601 dc and ac characteristics 51 7 dc and ac characteristics this section summarizes the operating me asurement conditions and the dc and ac characteristics of the de vice. the parameters in table 5 that follow are derived from tests performed under the measurement conditions summarized in table 4 . designers should check that the operating condit ions in their circuit match the operating conditions when relying on the quoted parameters. table 4. operating and ac measurement conditions parameter condition unit v cc supply voltage 1.6 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c input rise and fall times _ 5ns table 5. dc and ac characteristics symbol parameter test condition (1) min. typ. (2) max. unit v cc supply voltage 1.6 5.5 v i cc supply current v cc = 3.6 v, no load 6.0 8.0 a standby mode, enable deasserted, v cc = 3.6 v 0.6 1.0 a v th+ power-on lockout voltage (see table 10 for detailed listing) 2.40 2.50 2.60 v 3.00 3.10 3.20 3.20 3.30 3.40 3.29 3.40 3.51 3.39 3.50 3.61 v hyst threshold hysteresis (see table 10 for detailed listing) 200 mv 500 v th? forced power-off voltage (see table 10 for detailed listing) v th+ ? v hyst v t th? undervoltage detection to int delay v cc 2.0 v203244ms t on_blank blanking period (see table 10 for detailed listing) (3) 1.4 2.2 3.0 s 5.6 8.8 12.0 11.2 17.6 24.0 rst assertion to en (en ) assertion delay during power-up v cc = 3.6 v 100 ns
dc and ac characteristics stm6600, stm6601 40/52 docid15453 rev 12 pb v il input low voltage v cc 2.0 v, enable asserted 0.99 v v ih input high voltage v cc 2.0 v, enable asserted 1.05 v t debounce debounce period v cc 2.0 v203244ms r pb internal pull-up resistor v cc = 5.5 v, input asserted 65 100 135 k sr v il input low voltage 0.99 v v ih input high voltage 1.05 v t debounce debounce period 20 32 44 ms r sr (4) internal pull-up resistor v cc = 5.5 v, input asserted 65 100 135 k pb out v ol output low voltage v cc = 2 v, i sink = 1 ma, pb out asserted 0.3 v pb out leakage current v pbout = 3 v, pb out open drain ?0.1 +0.1 a vcc lo v ol output low voltage v cc = 2 v, i sink = 1 ma, vcc lo asserted 0.3 v vcc lo leakage current v vcclo = 3 v, vcc lo open drain ?0.1 +0.1 a ps hold v il input low voltage v cc 2.0 v0.99v v ih input high voltage v cc 2.0 v1.05 v glitch immunity 1 80 s ps hold leakage current v pshold = 0.6 v ?0.1 0.1 a ps hold to enable propagation delay 30 s r pshold pull-down resistor connected internally during power-up v pshold = 5.5 v 195 300 405 k table 5. dc and ac characteristics (continued) symbol parameter test condition (1) min. typ. (2) max. unit
docid15453 rev 12 41/52 stm6600, stm6601 dc and ac characteristics 51 c srd i srd c srd charging current 100 150 200 na v srd c srd voltage threshold v cc = 3.6 v, load on v ref pin 100 k and mandatory 1 f capacitor, t a = 25 c 1.5 v t srd additional smart reset ? delay time external c srd connected 10 s/f en, en v ol output low voltage v cc = 2 v, i sink = 1 ma, enable asserted 0.3 v v oh (5) output high voltage v cc = 2 v, i source = 1 ma, enable asserted v cc ? 0.3 v t en_off (6) enable off to enable on v cc 2.0 v406488ms en, en leakage current v en = 2 v, enable open drain ?0.1 +0.1 a rst v ol output low voltage v cc = 2 v, i sink = 1 ma, rst asserted 0.3 v t rec rst pulse width v cc 2.0 v 240 360 480 ms rst leakage current v rst = 3v ?0.1 +0.1 a int v ol output low voltage v cc = 2 v, i sink = 1 ma, int asserted 0.3 v t int _min minimum int pulse width v cc 2.0 v203244ms int leakage current v int = 3 v ?0.1 +0.1 a v ref v ref 1.5 v voltage reference v cc = 3.6 v, load on v ref pin 100 k and mandatory 1 f capacitor, t a = 25 c 1.485 ?1% 1.5 1.515 +1% v 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 1.6 v to 5.5 v (except where noted). 2. typical values are at t a = +25 c. 3. this blanking time allows the pr ocessor to start up correctly (see figure 7 , 8 , 9 , 10 , 11 , 12 ). 4. the internal pull-up resistor connected to the sr input is optional (see table 10 for detailed device options). 5. valid for push-pull only. 6. minimum delay time between enable deasse rtion and enable reassertion, allowing the application to complete the power-down properly. pb is ignored during this period. table 5. dc and ac characteristics (continued) symbol parameter test condition (1) min. typ. (2) max. unit
package mechanical data stm6600, stm6601 42/52 docid15453 rev 12 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark.
docid15453 rev 12 43/52 stm6600, stm6601 package mechanical data 51 figure 41. tdfn12 (2 x 3 mm) package outline table 6. tdfn12 (2 x 3 mm) package mechanical data symbol mm inches min. typ. max. min. typ. max. a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0. 05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 d 3.00 bsc 0.118 e 2.00 bsc 0.079 e 0.50 0.020 l 0.45 0.55 0.65 0.018 0.022 0.026 e 12 (d/2xe/2) index area l bottom view 7 pin#1 id 1 b 6 e seating top vi ew a a1 side view plane 2x d (d/2xe/2) index area 0.10 c 0.10 c 0.10 c 0.10 c a b c b a 0.08 c 8070542_a
package mechanical data stm6600, stm6601 44/52 docid15453 rev 12 figure 42. tdfn12 (2 x 3 mm) recommended footprint note: drawing not to scale. $0 [ [ [ [ 'lphqvlrqv pp lqfkhv [ [ [ [
docid15453 rev 12 45/52 stm6600, stm6601 package mechanical data 51 figure 43. carrier tape for tdfn12 (2 x 3 mm) package t k 0 p 1 a 0 b 0 p 2 p 0 center lines of cavity w e f d top cover tape user direction of feed am0 3 07 3 v1 table 7. carrier tape dimensions for tdfn12 (2 x 3 mm) package package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty. tdfn12 12.00 0.30 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 5.50 0.05 2.30 0.10 3.20 0.10 1.10 0.01 4.00 0.10 0.30 0.05 mm 3000
part numbering stm6600, stm6601 46/52 docid15453 rev 12 9 part numbering table 8. stm6600 ordering information scheme example: stm660 0 f q 2 4 dm 6 f device type stm660 startup process 0: pb must be held low until the ps hold confirmation input and output types (1) a: active high en output, long push asserts rst , pull-up on sr b: active low en output, long push asserts rst , pull-up on sr c: active high en output, long push deasserts en, pull-up on sr d: active low en output, long push deasserts en , pull-up on sr e: active high en output, long push asserts rst , no resistor on sr f: active low en output, long push asserts rst , no resistor on sr g: active high en output, long push deasserts en, no resistor on sr h: active low en output, long push deasserts en , no resistor on sr v th+ threshold voltage (1) a: 2.50 v q: 3.30 v s: 3.40 v u: 3.50 v v hyst voltage hysteresis (1) 2: 200 mv 5: 500 mv t on_blank blanking period (1) 2: 1.4 s (min.) 4: 5.6 s (min.) 5: 11.2 s (min.)
docid15453 rev 12 47/52 stm6600, stm6601 part numbering 51 package dm: tdfn12 temperature range 6: ?40 c to +85 c shipping method f: ecopack ? package, tape and reel 1. other options are offered. minimum order quantities may appl y. please contact local st sales office for availability. table 8. stm6600 ordering information scheme (continued) example: stm660 0 f q 2 4 dm 6 f
part numbering stm6600, stm6601 48/52 docid15453 rev 12 table 9. stm6601 ordering information scheme example: stm660 1 g u 2 b dm 6 f device type stm660 startup process 1: pb can be released before the ps hold confirmation input and output types (1) a: active high en output, long push asserts rst , pull-up on sr b: active low en output, long push asserts rst , pull-up on sr c: active high en output, long push deasserts en, pull-up on sr d: active low en output, long push deasserts en , pull-up on sr g: active high en output, long push deasserts en, no resistor on sr v th+ threshold voltage (1) a: 2.50 v m: 3.10 v q: 3.30 v s: 3.40 v u: 3.50 v v hyst voltage hysteresis (1) 2: 200 mv t on_blank blanking period (1) b: 1.4 s (min.) d: 5.6 s (min.) package dm: tdfn12 temperature range 6: ?40 c to +85 c shipping method f: ecopack ? package, tape and reel 1. other options are offered. minimum order quantities may appl y. please contact local st sales office for availability.
docid15453 rev 12 49/52 stm6600, stm6601 product selector 51 10 product selector table 10. stm6600 product selector full part number en or en (1) 1. en (or en ) output is push-pull. rst , int , pb out and vcc lo outputs are open drain. after long push (2) 2. after t srd expires through long push, either device reset (rst ) will be activated for t rec (240 ms min.) or the en (or en ) pin will be deasserted. the additional smart reset ? delay time, t srd , can be adjusted by the user at 10 s/f (typ.) by connecting the external capacitor to the c srd pin. internal resistor on sr input power-on lockout voltage v th+ (v) forced power-off voltage v th- (v) t on_blank (s) at startup (min.) t on_blank (s) at reset (min.) top marking (3) 3. where ?p? = assembly plant, ?y? = assembly year (0 to 9) and ?ww? = assembly work week (01 to 52). stm6600as24dm6f en rst pull-up 3.40 3.20 5.6 5.6 pyww as24 stm6600bq24dm6f en rst pull-up 3.30 3.10 5.6 5.6 pyww bq24 stm6600cs25dm6f en en pull-up 3.40 3.20 11.2 ? pyww cs25 stm6600da55dm6f en en pull-up 2.50 2.00 11.2 ? pyww da55 STM6600DQ25DM6F en en pull-up 3.30 3.10 11.2 ? pyww dq25 stm6600du25dm6f en en pull-up 3.50 3.30 11.2 ? pyww du25 stm6600es24dm6f (4) 4. please contact local st sale s office for availability. en rst ? 3.40 3.20 5.6 5.6 pyww es24 stm6600fq24dm6f (4) en rst ? 3.30 3.10 5.6 5.6 pyww fq24 stm6600gs22dm6f (4) en en ? 3.40 3.20 1.4 ? pyww gs22 stm6600gs25dm6f (4) en en ? 3.40 3.20 11.2 ? pyww gs25 stm6600gu22dm6f (4) en en ? 3.50 3.30 1.4 ? pyww gu22 stm6600ha55dm6f (4) en en ? 2.50 2.00 11.2 ? pyww ha55 stm6600hq25dm6f (4) en en ? 3.30 3.10 11.2 ? pyww hq25 stm6600hu25dm6f (4) en en ? 3.50 3.30 11.2 ? pyww hu25
product selector stm6600, stm6601 50/52 docid15453 rev 12 table 11. stm6601 product selector full part number en or en (1) 1. en (or en ) output is push-pull. rst , int , pb out and vcc lo outputs are open drain. after long push (2) 2. after t srd expires through long push, either device reset (rst ) will be activated for t rec (240 ms min.) or the en (or en ) pin will be deasserted. the additional smart reset ? delay time, t srd , can be adjusted by the user at 10 s/f (typ.) by connecting the external capacitor to the c srd pin. internal resistor on sr input power-on lockout voltage v th+ (v) forced power-off voltage v th- (v) t on_blank (s) at startup (min.) t on_blank (s) at reset (min.) top marking (3) 3. where ?p? = assembly plant, ?y? = assembly year (0 to 9) and ?ww? = assembly work week (01 to 52). stm6601aq2bdm6f en rst pull-up 3.30 3.10 1.4 1.4 pyww aq2b stm6601au2ddm6f en rst pull-up 3.50 3.30 5.6 5.6 pyww au2d stm6601bm2ddm6f en rst pull-up 3.10 2.90 5.6 5.6 pyww bm2d stm6601bs2bdm6f en rst pull-up 3.40 3.20 1.4 1.4 pyww bs2b stm6601ca2bdm6f en en pull-up 2.60 2.40 1.4 ? pyww ca2b stm6601cm2ddm6f en en pull-up 3.10 2.90 5.6 ? pyww cm2d stm6601cq2bdm6f en en pull-up 3.30 3.10 1.4 ? pyww cq2b stm6601cu2bdm6f en en pull-up 3.50 3.30 1.4 ? pyww cu2b stm6601ds2bdm6f en en pull-up 3.40 3.20 1.4 ? pyww ds2b stm6601gu2bdm6f (4) 4. please contact local st sale s office for availability. en en ? 3.50 3.30 1.4 ? pyww gu2b
docid15453 rev 12 51/52 stm6600, stm6601 revision history 51 11 revision history table 12. document revision history date revision changes 04-mar-2009 1 initial release. 05-jun-2009 2 updated text in section 2 , section 3 , figure 11 , 12 ; updated figure 1 , 7 , 9 , 14 , 18 , 19 , 43 , table 3 , 5 , 8 , 9 , 10 ; added figure 8 , 10 , ta ble 7 ; reformatted document. 23-jul-2009 3 updated text in features , table 1 , 8 , 9 , and 10 ; reformatted document. 22-oct-2009 4 updated section 2 , ta ble 5 , table 10 , figure 1 , 7 , 8 , 9 , 10 , 11 , 12 , 14 , 18 , title of section 10 ; added section 5: typical operating characteristics ( figure 23 through 40 ); document status upgraded to full datasheet. 25-jan-2010 5 updated figure 6 , section 2 , ta ble 5 ; textual update to ?smart reset ? ?. 13-apr-2010 6 updated figure 1 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , section 2 , section 3 , ta ble 3 , 5 , 8 , 9 , 10 . 07-jun-2010 7 reformatted figure 1 and figure 42 , corrected typo in section 3 , added option a to table 8 , updated table 10 and separated table 10 to table 10 and ta ble 11 . 10-sep-2010 8 updated standby current to 0.6 a throughout datasheet; removed footnote 2 of figure 14 ; updated table 8 , 9 , 11 ; minor textual updates. 24-feb-2011 9 updated table 11 - removed footnote 4. 12-may-2011 10 updated table 8 , table 10 and table 11 , minor text and typo modifications throughout document. 26-jun-2012 11 updated section 1: description , ?sr - smart reset? button input? in section 2: pin descriptions and ?hardware reset or power-down while system not responding? in section 3: operation , added cross-references in section 6: maximum ratings and section 7: dc and ac characteristics . 13-oct-2014 12 table 9 : added ?a? (2.50 v) to v th+ threshold voltage table 11 : added new full part number
stm6600, stm6601 52/52 docid15453 rev 12 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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